Syllabus and general information for MC48: Computer Organization (Fall 1998)


MC48 will cover the architecture and organization of computer hardware. We will look at the MIPS architecture as a representative modern RISC architecture, and do some assembly language programming for that architecture. We'll see how numbers are represented within a computer and how the circuits that perform arithmetic operations on those numerals are organized. With a high-level overview of digital logic design to support us, we'll look at how the datapaths and control circuits of processors are designed, and in particular we'll look in some depth at pipelined processor design, which is the key organizational principle at work in most present-day processors. We'll examine the use of memory hierarchy (cache memory and virtual memory) to provide the illusion of a large fast memory from the reality of limited fast memory plus a larger but slower memory. We'll look at input/output devices and buses, and at parallel computers. Throughout the course there will be an emphasis on the quantitative performance characteristics of computer systems; we'll look at the influence of architecture and organization on performance, and take an introductory look at the empirical and analytical tools appropriate to the study of performance. Performance measurement will be one of the main themes reinforced through the lab assignments; the other will be assembly language programming.

Office hours

I will be available in my office (OHS 303) 8:00-8:50 Tuesdays, 10:30-12:20 Wednesdays, 1:30-2:20 Fridays, and by appointment. You may send me electronic mail at or call me at extension 7466. I'll try to put any temporary updates to my office hours on my web page and any long-term updates on my on-line schedule, so check there if in doubt.

World Wide Web

All course handouts will be available through my World Wide Web page, and some supplementary materials such as code to use as a starting point in assignments may be available there as well. The URL for this course is


Our text will be the second edition of Computer Organization and Design: The Hardware/Software Interface by David A. Patterson and John L. Hennessy, published by Morgan Kaufmann.


Normally labs will be held on Mondays (and classes on the other four days), but there are four Wednesdays and one Friday when we'll also be in the lab; these are marked in the syllabus. We'll also do a class rather than a lab on two Mondays. Again, these are marked in the syllabus. Labs will be held in the OHS 326 lab, though we may need to spill over into the 329 lab a bit for those labs we do individually. Labs 0 and 5 will actually be special one-day demonstration experiences not requiring lab reports; only labs 1 through 4 will be ``real labs'' with reports.


The two intra-term exams will be conducted on October 8th and November 17th. The final exam will be as scheduled by the registrar; tentatively 10:30-12:30 on December 16th.


Students are encouraged to discuss the course, including issues raised by the assignments. However, the solutions to assignments should be individual original work unless otherwise specified. If an assignment makes you realize you don't understand the material, ask a fellow student a question designed to improve your understanding, not one designed to get the assignment done. To do otherwise is to cheat yourself out of understanding, as well as to be intolerably dishonorable.

Any substantive contribution to your solution by another person or taken from a publication should be properly acknowledged in writing. Failure to do so is plagiarism and will necessitate disciplinary action.

The same standards regarding plagiarism apply to team projects as to the work of individuals, except that the author is now the entire team rather than an individual. Anything taken from a source outside the team should be be properly cited.

One additional issue that arises from the team authorship of project reports is that all team members must stand behind all reports bearing their names. All team members have quality assurance responsibility for the entire project. If there is irreconcilable disagreement within the team it is necessary to indicate as much in the reports; this can be in the form of a ``minority opinion'' or ``dissenting opinion'' section where appropriate.

Late assignments

All homework and lab assignments are due at the beginning of class on the day indicated. Late assignments will be penalized by one ``grade notch'' (such as A to A- or A- to B+) for each weekday late or fraction thereof. However, no late assignments will be accepted after graded assignments are handed back.

If you are too sick to complete an assignment on time, you will not be penalized. Simply write ``late due to illness'' at the top of the assignment, sign your name and hand it in. Other circumstances will be evaluated on a case-by-case basis.

Grade changes

Please point out any arithmetic or clerical error I make in grading, and I will gladly fix it. You may also request reconsideration if I have been especially unjust.


I will provide you with a letter grade on each homework and lab assignment and on each test, in addition to the mid-term and final grades, so that you may keep track of your performance. As a guideline, the components will contribute in the following proportion to the final grade: However, I reserve the right to subjectively adjust your final grade. Please see me if you have any question how you stand. Class participation is not graded; however, it allows you to find and repair the gaps in your understanding before doing the homework or exam, and thus can dramatically improve your grade.

Style guidelines

All homework and lab reports should be readily readable, and should not presuppose that I already know what you are trying to say. In particular: Be sure your assignments are always stapled together and that your name is always on them.


Please contact me immediately if you have special physical circumstances, e.g. impaired vision, which may affect the accessibility of any course components. I will do my best to facilitate necessary arrangements or resources.


A single number in the reading column means to read that entire chapter. When a reading is indicated as going to a particular page number, it means up to the first heading on that page. The same section number on the next class day then indicates to finish the section.

This is my best guess as to the rate at which we will cover material. However, don't be shocked if I have to pass out one or more revised syllabi.
9/101Computer abstractions and technology

9/14Lab 0: Under the hood
9/153.1-3.5InstructionsHW 1
9/163.6-3.7Procedures and strings in assembly
9/173.8-3.9More on assembly programming
9/183.10-3.11Assembly programming examples

9/21Lab 1: Elementary assembly programming
9/223.12-3.15Yet more on assembly language
9/234.1-4.4Two's complement, addition, and subtractionHW 2
9/244.5Arithmetic Logic Unit

9/28Lab 1 (continued)
9/294.7DivisionHW 3
9/304.8Floating-point arithmetic
10/14.9-4.12More on arithmetic
10/2Lab 1 (concludes) (a Friday lab)

10/5Review; catch-up (class instead of lab)Lab 1
10/8Intra-term exam 1
10/9B.1-B.3Combinational logic

10/12Lab 2: More advanced assembly programming
10/13B.4-B.6Sequential logic
10/145.1-5.2A simple datapath
10/155.3-p. 371A single-cycle processor
10/165.3More on the single-cycle processor

10/19Lab 2 (continued)
10/205.4A multiple-cycle processorHW 4
10/21More on the multiple-cycle processor
10/225.5-5.9Microprogramming; exceptions

10/27C.1-C.4Mapping control to hardware
10/28Lab 2 (continued) (a Wednesday lab)
10/306.2A pipelined datapathHW 5

11/2Lab 2 (concludes)
11/36.3Pipelined control
11/46.4ForwardingLab 2
11/66.6-6.7Control hazards

11/9Lab 3: Measuring processor architectures' performanceHW 6
11/106.8-6.9Superscalar and advanced pipelining
11/11Lab 3 (continued) (a Wednesday lab)
11/126.10-6.12More on pipelining
11/13Review; catch-up

11/16Lab 3 (concludes)
11/17Intra-term exam 2
11/197.3Cache performanceLab 3
11/207.4Virtual memory

11/23Lab 4: Cache simulation
11/247.5Memory hierarchies
11/257.6-7.9Example memory hierarchiesHW 7

11/30Lab 4 (continued)
12/18.1-8.3Input/output devices
12/2Lab 4 (concludes) (a Wednesday lab)
12/48.5-8.11Interfacing input/output

12/79.1-9.3Bus-based MIMD architectures (class instead of lab)Lab 4
12/89.4-9.6Network-based MIMD architectures
12/9Lab 5: NOW parallelism demo (a Wednesday lab)
12/109.7-9.10More on multiprocessors
12/11Review; catch-up; evaluationHW 8

12/16Final exam, 10:30am (tentative)

Course web site:
Instructor: Max Hailperin <>