MC48 Homework 4 (Fall 1998)
Due: October 20, 1998

Design a PLA with four inputs, X_{3},
X_{2}, X_{1}, and
X_{0}, and two outputs D_{3} and
D_{5}. The four inputs should be considered as
forming a fourbit unsigned number,
X_{3}X_{2}X_{1}X_{0},
with X_{3} as the most significant bit. The
D_{3} output should be asserted if and only if that
number is divisible by 3. Similarly, the D_{5}
output should be asserted if and only if the input number is divisible
by 5.

Do exercise 5.6 on page 427.

Do exercise 5.10 on page 428. The exercise says "consider both
datapaths." By "both" they mean the singlecycle datapath from section 5.3
and the multicycle one from section 5.4. For this homework, you should
only deal with the singlecycle one from section 5.3.
Instructor: Max Hailperin