When turning in a homework problem, be sure to indicate the exercise number. These will be the reference numbers I use in reporting back your standing on the homework.
Exercise 5.3.1 on page 550, using only data set (a).
Exercise 5.3.2 on page 550, using only data set (a).
Exercises 5.4.1-3 on page 551, using only data set (b). In the index column of the data table, "15" should actually be "5". Assume byte addressing.
Exercises 5.6.1-3 on page 553. Assume byte addressing
Exercise 5.8.1 on page 555, using only data set (a).
Exercise 5.x1: Page 540 shows the AMD Opteron X4 processor as having four TLBs per core: separate L1 (level 1) TLBs for instruction and data accesses, each of which are 48-entry fully associative TLBs, and separate L2 TLBs for instruction and data accesses, each of which are 512 entry set associative TLBs. By analogy with material earlier in the chapter regarding caches, answer the following questions:
What is the advantage of using separate TLBs for instruction and data accesses, rather than unified TLBs containing 96 entries at L1 and 1024 entries at L2?
What is the advantage of including the 512-entry L2 TLBs, rather than moving directly to the page table after the 48-entry L1 TLBs?
What is the advantage of including the 48-entry L1 TLBs, rather than moving directly to a 512-entry (or even 560 entry) TLB?
What is the advantage of having the L1 TLBs be fully associative rather than four-way set associative?
What is the advantage of having the L2 TLBs be set associative rather than fully associative? Why is this different than for the L1 TLBs?
Instructor: Max Hailperin