# MCS-284 Chapter 4 Homework

When turning in a homework problem, mark it with the exercise number shown in bold here. These will be the reference numbers I use in reporting back your standing on the homework.

• 4.1.1-3 on page 409 using both the a and the b instructions. Use Figure 4.17 instead of Figure 4.2. In parts 2 and 3, focus your attention on the seven kinds of blocks listed at the top of page 410. Distinguish the two Add blocks as "left adder" and "right adder." Distinguish the Mux blocks by naming the related control signal ("RegDst Mux," "ALUSrc Mux," "Branch Mux," and"MemtoReg Mux").

• 4.1.4-6 on page 410 using the b latencies only. Use Figure 4.17 instead of Figure 4.2. The latencies listed for Regs and D-Mem apply to either reading from or writing to the resource. In part 5, the instruction is LW, not LD.

• 4.9.2-4 on page 417 using both the a and the b instructions. (For the b instruction, you may substitute beq for bne.) In part 4, use these together with all three control signals mentioned (RegDst, MemRead, and RegWrite). In any part, if there is more than one possible answer, list them all. Note with regard to the caption on Figure 4.14 (p. 319) that the last line should refer to adding to PC+4, not the original PC value.

• 4.13.2,3,5 on pages 420-421 using instruction sequence a only. Assume that even when there is no forwarding, the register file is written in the first half of each clock cycle and read in the second half. (To clarify the problem number: I am assigning parts 2, 3, and 5 of 4.13, using instruction sequence a.)

• 4.14.1 on pages 421-422 using instruction sequence b only.

• 4.15.1-2 on page 423 using instruction sequence b only. Also, show how Figure 4.49 (page 360) would be modified; show both how existing control signals would be set for the new instruction and how any new control signals would be set for each instruction. Where a control signal can be shown as X (don't care), please do so, rather than showing an arbitrary 0 or 1.

• 4.35.1-2 on page 443 using data from row a only. Note that part 2 is independent from part 1; it asks how much faster the overall program execution would be with 4 delay slots (and a bunch of stalls) versus with no delay slots (and even more stalls).

Instructor: Max Hailperin