Syllabus and general information for MCS-284: Computer Organization (Fall 2000)

Overview

MCS-284 will cover the architecture and organization of computer hardware. We will look at the MIPS architecture as a representative modern RISC architecture, and do some assembly language programming for that architecture. We'll see how numbers are represented within a computer and how the circuits that perform arithmetic operations on those numerals are organized. With a high-level overview of digital logic design to support us, we'll look at how the datapaths and control circuits of processors are designed, and in particular we'll look in some depth at pipelined processor design, which is the key organizational principle at work in most present-day processors. We'll examine the use of memory hierarchy (cache memory and virtual memory) to provide the illusion of a large fast memory from the reality of limited fast memory plus a larger but slower memory. We'll look at input/output devices and buses, and at parallel computers. Throughout the course there will be an emphasis on the quantitative performance characteristics of computer systems; we'll look at the influence of architecture and organization on performance, and take an introductory look at the empirical and analytical tools appropriate to the study of performance. Performance measurement will be one of the main themes reinforced through the lab assignments; the other will be assembly language programming.

Office hours

I will be available in my office (OHS 303) 2:30-3:20 Tuesdays, 10:30-11:20 Wednesdays, 9:00-9:50 Thursdays, 10:30-11:20 Fridays, and by appointment. Or try your luck: just stop by and see whether my door is open. However, I will have no office hours the week of September 18-22 (sorry). You may send me electronic mail at max@gustavus.edu or call me at extension 7466. I'll try to put any updates to my office hours on my web page, so check there if in doubt.

World Wide Web

All course materials will be available through my World Wide Web page. The URL for this course is http://www.gustavus.edu/~max/courses/F2000/MCS-284/. After this syllabus I will give hardcopy handouts only to those students who want them.

Text

Our text will be the second edition of Computer Organization and Design: The Hardware/Software Interface by David A. Patterson and John L. Hennessy, published by Morgan Kaufmann.

Labs

Normally labs will be held on Wednesdays and classes on the other four days, but there are some exceptions; these are marked in the syllabus. Labs will be held in the OHS 326 lab. Lab 0 will actually be a special one-day demonstration experience not requiring a lab report; only labs 1 through 4 will be ``real labs'' with reports.

Attendance is mandatory for all lab days. (If you turn in a lab report early, you are excused from the remaining days devoted to that lab.) I will excuse up to three absences per student, for any reason. Use yours wisely. If you exceed this allowance, I may reduce your course grade by one letter grade.

Homework assignment policy

I will assign a collection of homework problems for each chapter. You may turn in any individual homework problem whenever you think you have it solved. I will return it to you as quickly as I can, but normally with only an indication of whether it is acceptable or needs more work. (Sometimes I may give a brief indication of what area it needs more work in.) If a problem needs more work, and you aren't sure what sort of work it still needs, you should treat that as an invitation to come talk with me about it. Once you've done the additional work, you may turn the problem in again. In fact, you may turn in each problem in as many times as you like, until it is marked as acceptable. Your grade for the homework portion of the course will be based on the fraction of homework problems that you eventually did acceptably.

Normally homework problems may be turned in at any time. However, if the class is not being responsible, and it looks like I may be faced with a flood of problems at the end of the semester, I may set due dates (always at least a week in the future). Also, if we would benefit from discussing a homework problem in class, I may issue a "last call" for solutions to that problem (again, at least a week in advance).

Unless I indicate that a particular problem must be done individually, you may work on any problem in a group of two or three students. One copy of the solution produced by the team should be turned in, with all team members names on it. Write "we all contributed fairly to this solution" and have all team members sign under that statement.

Tests

There will be two intra-term tests and a final exam, as shown on the syllabus below. (Note that the final exam will be as scheduled by the registrar. The date and time shown in the syllabus are the tentative projection from the registrar's office, but are subject to change by that office.)

Honor

Students are encouraged to discuss the course, including issues raised by the assignments. However, the solutions to assignments should be individual original work unless otherwise specified. If an assignment makes you realize you don't understand the material, ask a fellow student a question designed to improve your understanding, not one designed to get the assignment done. To do otherwise is to cheat yourself out of understanding, as well as to be intolerably dishonorable.

Any substantive contribution to your solution by another person or taken from a publication should be properly acknowledged in writing. Failure to do so is plagiarism and will necessitate disciplinary action.

The same standards regarding plagiarism apply to team projects as to the work of individuals, except that the author is now the entire team rather than an individual. Anything taken from a source outside the team should be be properly cited.

One additional issue that arises from the team authorship of project reports is that all team members must stand behind all reports bearing their names. All team members have quality assurance responsibility for the entire project. If there is irreconcilable disagreement within the team it is necessary to indicate as much in the reports; this can be in the form of a ``minority opinion'' or ``dissenting opinion'' section where appropriate.

Late lab assignments

All lab assignments are due at the beginning of class on the day indicated. Late assignments will be penalized by one ``grade notch'' (such as A to A- or A- to B+) for each weekday late or fraction thereof. However, no late assignments will be accepted after graded assignments are handed back.

If you are too sick to complete an assignment on time, you will not be penalized. Simply write ``late due to illness'' at the top of the assignment, sign your name and hand it in. Other circumstances will be evaluated on a case-by-case basis.

Grade changes

Please point out any arithmetic or clerical error I make in grading, and I will gladly fix it. You may also request reconsideration if I have been especially unjust.

Grading

The course components will contribute to your grade in the following proportion:

Test 1: 15%
Test 2: 15%
Final exam: 20%
Homework: 26% (based on fraction done: see above)
Labs: 24% (4 @ 6% each)

However, I reserve the right to subjectively adjust your final grade. Please see me if you have any question how you stand. Class participation is not graded; however, it allows you to find and repair the gaps in your understanding before doing the assignments, and thus can dramatically improve your grade. You are responsible for all course material, whether or not you are present when it was covered or distributed.

Style guidelines

All assignments should be readily readable, and should not presuppose that I already know what you are trying to say. Use full English sentences where appropriate (namely almost everywhere) and clear diagrams, programs, etc. Remember that your goal is to communicate clearly, and that the appearance of these technical items plays a role in this communication process. Be sure your assignments are always stapled together and that your name is always on them.

Accessibility

Please contact me immediately if you have a learning or physical disability requiring accommodation.

Syllabus

A single number in the reading column means to read that entire chapter. When a reading is indicated as going to a particular page number, it means up to the first heading on that page. The same section number on the next class day then indicates to finish the section.

This is my best guess as to the rate at which we will cover material. However, don't be shocked if I have to pass out one or more revised syllabi.

Date Reading Topic Due
9/6 Introduction (class instead of lab)
9/7 1 Computer abstractions and technology
9/8 2 Performance

9/11 article More on performance
9/12 3.1-3.5 Instructions
9/13 3.6-3.7 Procedures and strings in assembly (class instead of lab)
9/14 3.8-3.9 More on assembly programming
9/15 A.1-A.6,A.9 Assembly programming tools

9/18 No class
9/19 3.10-3.11 Assembly programming examples
9/20 Lab 0: Under the hood
9/21 No class
9/22 No class

9/25 Lab 1: Elementary assembly programming (a Monday lab)
9/26 3.12-3.15 Yet more on assembly language
9/27 Lab 1 (continued)
9/28 4.1-4.4 Two's complement, addition, and subtraction
9/29 More on arithmetic

10/2 Lab 1 (concludes) (a Monday lab)
10/5 B.1-B.3 Combinational logic Lab 1
10/6 B.4-B.6 Sequential logic

10/9 Review; catch-up
10/10 Intra-term test 1
10/11 Lab 2: More advanced assembly programming
10/12 5.1-5.2 A simple datapath
10/13 5.3-p. 371 A single-cycle processor

10/16 5.3 More on the single-cycle processor
10/17 5.4 A multiple-cycle processor
10/18 Lab 2 (continued)
10/19 More on the multiple-cycle processor

10/24 5.5-5.9 Microprogramming; exceptions
10/25 Lab 2 (continued)
10/26 6.1 Pipelining
10/27 6.2 A pipelined datapath

10/30 6.3 Pipelined control
10/31 6.4 Forwarding
11/1 Lab 2 (concludes)
11/2 6.5 Stalls
11/3 6.6-6.7 Control hazards Lab 2

11/6 Lab 3: Measuring processor architectures' performance (a Monday lab)
11/7 6.8-6.9 Superscalar and advanced pipelining
11/8 Lab 3 (continued)
11/9 6.10-6.12 More on pipelining
11/10 Review; catch-up

11/13 Intra-term test 2
11/14 7.1-7.2 Caches
11/15 Lab 3 (concludes)
11/16 7.3 Cache performance
11/17 7.4 Virtual memory Lab 3

11/20 7.5 Memory hierarchies
11/21 7.6-7.9 Example memory hierarchies
11/22 Lab 4: Cache simulation

11/27 Lab 4 (continued) (a Monday lab)
11/28 4.5 Arithmetic Logic Unit
11/29 Lab 4 (continued)
11/30 4.8 Floating-point arithmetic
12/1 More on arithmetic

12/4 8.1-8.3 Input/output devices
12/5 8.4 Buses
12/6 Lab 4 (concludes)
12/7 8.5-8.11 Interfacing input/output
12/8 9.1-9.3 Bus-based MIMD architectures Lab 4

12/11 9.4-9.6 Network-based MIMD architectures
12/12 9.7-9.10 More on multiprocessors
12/13 Review; catch-up; evaluation (class instead of lab)

Date	Reading	Topic	Due
9/6		Introduction (class instead of lab)
9/7	1	Computer abstractions and technology
9/8	2	Performance

9/11	article	More on performance
9/12	3.1-3.5	Instructions
9/13	3.6-3.7	Procedures and strings in assembly (class instead of lab)
9/14	3.8-3.9	More on assembly programming
9/15	A.1-A.6,A.9	Assembly programming tools

9/18		No class
9/19	3.10-3.11	Assembly programming examples
9/20		Lab 0: Under the hood
9/21		No class
9/22		No class

9/25		Lab 1: Elementary assembly programming (a Monday lab)
9/26	3.12-3.15	Yet more on assembly language
9/27		Lab 1 (continued)
9/28	4.1-4.4	Two's complement, addition, and subtraction
9/29		More on arithmetic

10/2		Lab 1 (concludes) (a Monday lab)
10/5	B.1-B.3	Combinational logic	Lab 1
10/6	B.4-B.6	Sequential logic

10/9		Review; catch-up
10/10		Intra-term test 1
10/11		Lab 2: More advanced assembly programming
10/12	5.1-5.2	A simple datapath
10/13	5.3-p. 371	A single-cycle processor

10/16	5.3	More on the single-cycle processor
10/17	5.4	A multiple-cycle processor
10/18		Lab 2 (continued)
10/19		More on the multiple-cycle processor

10/24	5.5-5.9	Microprogramming; exceptions
10/25		Lab 2 (continued)
10/26	6.1	Pipelining
10/27	6.2	A pipelined datapath

10/30	6.3	Pipelined control
10/31	6.4	Forwarding
11/1		Lab 2 (concludes)
11/2	6.5	Stalls
11/3	6.6-6.7	Control hazards	Lab 2

11/6		Lab 3: Measuring processor architectures' performance (a Monday lab)
11/7	6.8-6.9	Superscalar and advanced pipelining
11/8		Lab 3 (continued)
11/9	6.10-6.12	More on pipelining
11/10		Review; catch-up

11/13		Intra-term test 2
11/14	7.1-7.2	Caches
11/15		Lab 3 (concludes)
11/16	7.3	Cache performance
11/17	7.4	Virtual memory	Lab 3

11/20	7.5	Memory hierarchies
11/21	7.6-7.9	Example memory hierarchies
11/22		Lab 4: Cache simulation

11/27		Lab 4 (continued) (a Monday lab)
11/28	4.5	Arithmetic Logic Unit
11/29		Lab 4 (continued)
11/30	4.8	Floating-point arithmetic
12/1		More on arithmetic

12/4	8.1-8.3	Input/output devices
12/5	8.4	Buses
12/6		Lab 4 (concludes)
12/7	8.5-8.11	Interfacing input/output
12/8	9.1-9.3	Bus-based MIMD architectures	Lab 4

12/11	9.4-9.6	Network-based MIMD architectures
12/12	9.7-9.10	More on multiprocessors
12/13		Review; catch-up; evaluation (class instead of lab)

Course web site: http://www.gustavus.edu/~max/courses/F2000/MCS-284/
Instructor: Max Hailperin <max@gustavus.edu>