Syllabus and general information for MCS-284: Computer Organization (Fall 1999)

Overview

MCS-284 will cover the architecture and organization of computer hardware. We will look at the MIPS architecture as a representative modern RISC architecture, and do some assembly language programming for that architecture. We'll see how numbers are represented within a computer and how the circuits that perform arithmetic operations on those numerals are organized. With a high-level overview of digital logic design to support us, we'll look at how the datapaths and control circuits of processors are designed, and in particular we'll look in some depth at pipelined processor design, which is the key organizational principle at work in most present-day processors. We'll examine the use of memory hierarchy (cache memory and virtual memory) to provide the illusion of a large fast memory from the reality of limited fast memory plus a larger but slower memory. We'll look at input/output devices and buses, and at parallel computers. Throughout the course there will be an emphasis on the quantitative performance characteristics of computer systems; we'll look at the influence of architecture and organization on performance, and take an introductory look at the empirical and analytical tools appropriate to the study of performance. Performance measurement will be one of the main themes reinforced through the lab assignments; the other will be assembly language programming.

Office hours

I will be available in my office (OHS 303) 11:30-12:20 Tuesdays, 2:30-3:20 Wednesdays, 9:00-9:50 Thursdays, 1:30-2:20 Fridays, and by appointment. Or try your luck: just stop by and see whether my door is open. You may send me electronic mail at max@gustavus.edu or call me at extension 7466. I'll try to put any updates to my office hours on my web page, so check there if in doubt.

World Wide Web

All course materials will be available through my World Wide Web page. The URL for this course is http://www.gustavus.edu/~max/courses/F1999/MCS-284/. After this syllabus I will give hardcopy handouts only to those students who want them.

Text

Our text will be the second edition of Computer Organization and Design: The Hardware/Software Interface by David A. Patterson and John L. Hennessy, published by Morgan Kaufmann.

Labs

Normally labs will be held on Wednesdays and classes on the other four days, but there are some exceptions; these are marked in the syllabus. Labs will be held in the OHS 326 lab. Lab 0 will actually be a special one-day demonstration experience not requiring a lab report; only labs 1 through 4 will be ``real labs'' with reports.

Tests

There will be two intra-term tests and a final exam, as shown on the syllabus below. (Note that the final exam will be as scheduled by the registrar. The date and time shown in the syllabus are the tentative projection from the registrar's office, but are subject to change by that office.)

Honor

Students are encouraged to discuss the course, including issues raised by the assignments. However, the solutions to assignments should be individual original work unless otherwise specified. If an assignment makes you realize you don't understand the material, ask a fellow student a question designed to improve your understanding, not one designed to get the assignment done. To do otherwise is to cheat yourself out of understanding, as well as to be intolerably dishonorable.

Any substantive contribution to your solution by another person or taken from a publication should be properly acknowledged in writing. Failure to do so is plagiarism and will necessitate disciplinary action.

The same standards regarding plagiarism apply to team projects as to the work of individuals, except that the author is now the entire team rather than an individual. Anything taken from a source outside the team should be be properly cited.

One additional issue that arises from the team authorship of project reports is that all team members must stand behind all reports bearing their names. All team members have quality assurance responsibility for the entire project. If there is irreconcilable disagreement within the team it is necessary to indicate as much in the reports; this can be in the form of a ``minority opinion'' or ``dissenting opinion'' section where appropriate.

Late assignments

All homework and lab assignments are due at the beginning of class on the day indicated. Late assignments will be penalized by one ``grade notch'' (such as A to A- or A- to B+) for each weekday late or fraction thereof. However, no late assignments will be accepted after graded assignments are handed back.

If you are too sick to complete an assignment on time, you will not be penalized. Simply write ``late due to illness'' at the top of the assignment, sign your name and hand it in. Other circumstances will be evaluated on a case-by-case basis.

Grade changes

Please point out any arithmetic or clerical error I make in grading, and I will gladly fix it. You may also request reconsideration if I have been especially unjust.

Grading

I will provide you with a letter grade on each homework and lab assignment and on each test, in addition to the mid-term and final grades, so that you may keep track of your performance. As a guideline, the components will contribute in the following proportion to the final grade:

20% lab assignments (4 @ 5% each)
40% homework (8 @ 5% each)
24% intra-term exams (2 @ 12% each)
16% final exam

However, I reserve the right to subjectively adjust your final grade. Please see me if you have any question how you stand. Class participation is not graded; however, it allows you to find and repair the gaps in your understanding before doing the homework or exam, and thus can dramatically improve your grade.

Style guidelines

All homework and lab reports should be readily readable, and should not presuppose that I already know what you are trying to say. Use full English sentences where appropriate (namely almost everywhere) and clear diagrams, programs, etc. Remember that your goal is to communicate clearly, and that the appearance of these technical items plays a role in this communication process. Be sure your assignments are always stapled together and that your name is always on them.

Accessibility

Please contact me immediately if you have a learning or physical disability requiring accommodation.

Syllabus

A single number in the reading column means to read that entire chapter. When a reading is indicated as going to a particular page number, it means up to the first heading on that page. The same section number on the next class day then indicates to finish the section.

This is my best guess as to the rate at which we will cover material. However, don't be shocked if I have to pass out one or more revised syllabi.

Date Reading Topic Due
9/8 Introduction (class instead of lab)
9/9 1 Computer abstractions and technology
9/10 2 Performance

9/13 More on performance
9/14 3.1-3.5 Instructions
9/15 Lab 0: Under the hood HW 1
9/16 3.6-3.7 Procedures and strings in assembly
9/17 3.8-3.9 More on assembly programming

9/20 A.1-A.6,A.9 Assembly programming tools
9/21 3.10-3.11 Assembly programming examples
9/22 Lab 1: Elementary assembly programming
9/23 3.12-3.15 Yet more on assembly language HW 2
9/24 4.1-4.4 Two's complement, addition, and subtraction

9/27 More on arithmetic
9/28 4.5 Arithmetic Logic Unit
9/29 Lab 1 (continued)
9/30 4.8 Floating-point arithmetic
10/1 More on arithmetic HW 3

10/4 Lab 1 (concludes) (a Monday lab)
10/7 Review; catch-up Lab 1
10/8 Intra-term exam 1

10/11 B.1-B.3 Combinational logic
10/12 B.4-B.6 Sequential logic
10/13 Lab 2: More advanced assembly programming
10/14 5.1-5.2 A simple datapath
10/15 5.3-p. 371 A single-cycle processor

10/18 5.3 More on the single-cycle processor
10/19 5.4 A multiple-cycle processor HW 4
10/20 Lab 2 (continued)
10/21 More on the multiple-cycle processor

10/26 5.5-5.9 Microprogramming; exceptions
10/27 Lab 2 (continued)
10/28 6.1 Pipelining
10/29 6.2 A pipelined datapath HW 5

11/1 6.3 Pipelined control
11/2 6.4 Forwarding
11/3 Lab 2 (concludes)
11/4 6.5 Stalls
11/5 6.6-6.7 Control hazards Lab 2

11/8 Lab 3: Measuring processor architectures' performance (a Monday lab)
11/9 6.8-6.9 Superscalar and advanced pipelining HW 6
11/10 Lab 3 (continued)
11/11 6.10-6.12 More on pipelining
11/12 Review; catch-up

11/15 Intra-term exam 2
11/16 7.1-7.2 Caches
11/17 Lab 3 (concludes)
11/18 7.3 Cache performance
11/19 7.4 Virtual memory Lab 3

11/22 7.5 Memory hierarchies
11/23 7.6-7.9 Example memory hierarchies
11/24 Lab 4: Cache simulation HW 7

11/29 Lab 4 (continued) (a Monday lab)
11/30 8.1-8.3 Input/output devices
12/1 Lab 4 (continued)
12/2 8.4 Buses
12/3 8.5-8.11 Interfacing input/output

12/6 9.1-9.3 Bus-based MIMD architectures HW 8
12/7 9.4-9.6 Network-based MIMD architectures
12/8 Lab 4 (concludes)
12/9 9.7-9.10 More on multiprocessors
12/10 Review; catch-up; evaluation Lab 4

12/15 Final exam, 8:00-10:00am (tentative)

Date	Reading	Topic	Due
9/8		Introduction (class instead of lab)
9/9	1	Computer abstractions and technology
9/10	2	Performance

9/13		More on performance
9/14	3.1-3.5	Instructions
9/15		Lab 0: Under the hood	HW 1
9/16	3.6-3.7	Procedures and strings in assembly
9/17	3.8-3.9	More on assembly programming

9/20	A.1-A.6,A.9	Assembly programming tools
9/21	3.10-3.11	Assembly programming examples
9/22		Lab 1: Elementary assembly programming
9/23	3.12-3.15	Yet more on assembly language	HW 2
9/24	4.1-4.4	Two's complement, addition, and subtraction

9/27		More on arithmetic
9/28	4.5	Arithmetic Logic Unit
9/29		Lab 1 (continued)
9/30	4.8	Floating-point arithmetic
10/1		More on arithmetic	HW 3

10/4		Lab 1 (concludes) (a Monday lab)
10/7		Review; catch-up	Lab 1
10/8		Intra-term exam 1

10/11	B.1-B.3	Combinational logic
10/12	B.4-B.6	Sequential logic
10/13		Lab 2: More advanced assembly programming
10/14	5.1-5.2	A simple datapath
10/15	5.3-p. 371	A single-cycle processor

10/18	5.3	More on the single-cycle processor
10/19	5.4	A multiple-cycle processor	HW 4
10/20		Lab 2 (continued)
10/21		More on the multiple-cycle processor

10/26	5.5-5.9	Microprogramming; exceptions
10/27		Lab 2 (continued)
10/28	6.1	Pipelining
10/29	6.2	A pipelined datapath	HW 5

11/1	6.3	Pipelined control
11/2	6.4	Forwarding
11/3		Lab 2 (concludes)
11/4	6.5	Stalls
11/5	6.6-6.7	Control hazards	Lab 2

11/8		Lab 3: Measuring processor architectures' performance (a Monday lab)
11/9	6.8-6.9	Superscalar and advanced pipelining	HW 6
11/10		Lab 3 (continued)
11/11	6.10-6.12	More on pipelining
11/12		Review; catch-up

11/15		Intra-term exam 2
11/16	7.1-7.2	Caches
11/17		Lab 3 (concludes)
11/18	7.3	Cache performance
11/19	7.4	Virtual memory	Lab 3

11/22	7.5	Memory hierarchies
11/23	7.6-7.9	Example memory hierarchies
11/24		Lab 4: Cache simulation	HW 7

11/29		Lab 4 (continued) (a Monday lab)
11/30	8.1-8.3	Input/output devices
12/1		Lab 4 (continued)
12/2	8.4	Buses
12/3	8.5-8.11	Interfacing input/output

12/6	9.1-9.3	Bus-based MIMD architectures	HW 8
12/7	9.4-9.6	Network-based MIMD architectures
12/8		Lab 4 (concludes)
12/9	9.7-9.10	More on multiprocessors
12/10		Review; catch-up; evaluation	Lab 4

12/15		Final exam, 8:00-10:00am (tentative)

Course web site: http://www.gustavus.edu/~max/courses/F1999/MCS-284/
Instructor: Max Hailperin <max@gustavus.edu>