MC48 Homework 4 (Fall 1998)

Due: October 20, 1998

1. Design a PLA with four inputs, X₃, X₂, X₁, and X₀, and two outputs D₃ and D₅. The four inputs should be considered as forming a four-bit unsigned number, X₃X₂X₁X₀, with X₃ as the most significant bit. The D₃ output should be asserted if and only if that number is divisible by 3. Similarly, the D₅ output should be asserted if and only if the input number is divisible by 5.
2. Do exercise 5.6 on page 427.
3. Do exercise 5.10 on page 428. The exercise says "consider both datapaths." By "both" they mean the single-cycle datapath from section 5.3 and the multicycle one from section 5.4. For this homework, you should only deal with the single-cycle one from section 5.3.

Instructor: Max Hailperin