Approximate Microprocessor Technology Trends
Every two or three years,
it used to be that
- there were 2× as many transistors:
- 2× as many logic transistors, and
- 2× as much cache memory (SRAM)
- the extra logic transistors improved the IPC 1.4×
- the transistor switching events per unit of energy improved 2.8×
- so even with 2× as many transistors, the frequency could improve 1.4× with the same power
- combining the IPC improvement and clock rate improvement, performance increased 2×
more recently,
- there were 2× as many transistors:
- 2× as many logic transistors, and
- 2× as much cache memory (SRAM)
- the transistor switching events per unit of energy only improved 2×
- so with 2× as many transistors, the frequency had to stay steady to use the same power
- that means increasing IPC 1.4× would yield a ho-hum 1.4× performance increase
- so instead the extra logic transistors were used for 2× the number of processing cores
- which increases the peak throughput 2×, provided all cores can be kept busy
- for applications where that works well, it even makes sense to undo earlier IPC improvements:
- use wimpier processing cores
- but more of them
and now we're in an era in which
- there are 2× as many transistors
- but the transistor switching events per unit of energy doesn't even improve 2×
- so to keep the power fixed, the number of actively used transistors can't go up 2×
- which means even the peak throughput can't go up 2×
- unless designers get clever about useful work per switching event
- which often means more specialized processing units
and looking to the future,
- finding ever more specialized units doesn't seem promising
- so perhaps we should rethink the "keep power fixed" part
- for example with computational sprinting