When turning in a homework problem, mark it with the exercise number shown in bold here. These will be the reference numbers I use in reporting back your standing on the homework.
4.1.1-3 on page 409 using both the a and the b instructions. Use Figure 4.17 (p. 322) instead of Figure 4.2. In parts 2 and 3, focus your attention on the eight kinds of blocks listed in Exercise 4.7 on page 415. Distinguish the two Add blocks as "left adder" and "right adder." Distinguish the Mux blocks by naming the related control signal ("RegDst Mux," "ALUSrc Mux," "Branch Mux," and"MemtoReg Mux").
4.7.1-3 on page 415 using the a latencies only. Use Figure 4.17 (p. 322) for reference. The latencies listed for Regs and D-Mem apply to either reading from or writing to the resource.
4.x1:
Suppose the designers of the next-generation MIPS architecture are considering adding two
instructions to the instruction set, sws and lws. The names of these
two instructions stand for Store Word Stepping and Load Word Stepping.
They behave just like the normal sw and lw instructions, except that
each of them also writes a new value into the base address register, found by adding the offset.
For example, the following two instructions:
sw $t0, 16($t1)
addiu $t1, $t1, 16
could be replaced with one:
sws $t0, 16($t1)
The machine-language format of the two new instructions uses the Rs, Rt, and Imm
fields in the same way as for sw and lw.
Modifying the textbook's processor designs to accommodate one of these instructions would require a change in the register file. (The other instruction could be accommodated using the existing register file.) Which instruction requires the register file change? What would the change be?
Make copies of the single-cycle datapath and control table, Figures 4.17 and 4.18 (pp. 322-323). Make any modifications necessary to add the two new instructions. If you add any new control signals to the datapath, add columns for them to the table and show the values in those new columns in all rows, old as well as new. If any of the control signals can be don't cares, show them as X, rather than arbitrarily filling in a 0 or 1.
4.x2: Suppose we execute the following sequence of instructions. During the first clock cycle, the first instruction is fetched from address 2000 in instruction memory:
lw $5, 8($4)
sub $4, $7, $3
sw $9, 4($8)
add $8, $2, $1
beq $5, $6, 1000
Suppose further that the following registers and data memory locations contain the specified values when execution starts:
| Number | Value |
|---|---|
| 1 | 10 |
| 2 | 20 |
| 3 | 30 |
| 4 | 40 |
| 5 | 50 |
| 6 | 60 |
| 7 | 70 |
| 8 | 80 |
| 9 | 90 |
| Address | Value |
|---|---|
| 24 | 17 |
| 28 | 42 |
| 44 | 13 |
| 48 | 79 |
| 84 | 22 |
| 88 | 28 |
Make a copy of Figure 4.51 (p. 362) and write onto as many of the lines as you can the value that will be there during the fifth clock cycle.
4.x3: For each of the following eight sequences of instructions, indicate whether the textbook's pipelined processor would use forwarding, stalling, both, or neither. As usual, we are assuming that registers are written in the first half of the clock cycle and read during the second half; this doesn't count as forwarding.
lw $1, 0($2) add $3, $1, $4 add $4, $5, $6 add $5, $6, $7
add $1, $2, $3 add $2, $3, $4 add $3, $4, $5 add $5, $4, $3
lw $1, 0($2) add $3, $4, $5 add $4, $5, $6 add $7, $1, $2
add $1, $2, $3 add $2, $3, $4 sw $1, 4($3) add $3, $4, $5
add $1, $2, $3 lw $4, 0($5) add $5, $6, $7 add $6, $4, $4
lw $1, 0($2) add $3, $2, $1 add $4, $5, $6 add $5, $1, $6
add $1, $2, $3 add $2, $3, $4 sw $3, 4($1) add $3, $4, $5
add $1, $2, $3 add $2, $3, $4 add $3, $4, $5 add $5, $1, $2
4.14.1 on pages 421-422 using instruction sequence b only.
4.15.1-2 on page 423 using instruction sequence b only. You can use Figure 4.51 (page 362) as your starting point. Also, show how Figure 4.49 (page 360) would be modified; show both how existing control signals would be set for the new instruction and how any new control signals would be set for each instruction. Where a control signal can be shown as X (don't care), please do so, rather than showing an arbitrary 0 or 1.
Instructor: Max Hailperin