MC48 Homework 5 (Fall 1996)

Due: November 1, 1996

1. (This is exercise 5.n3.) Suppose a machine were built according to the design of the multicycle datapath, but a mistake was made in the construction such that one of the control signals always remained 0. For each of the following control signals, explain which instructions (if any) would execute correctly on the defective machine, and which wouldn't. (In each case the defect is that the given control signal is permanently stuck at 0.)
   1. RegDst
   2. MemtoReg
   3. IorD
   4. ALUSrcA
2. (This is exercise 5.n4.) Do the previous exercise over, but assume that in each of the four defective machines the specified control signal is permanently stuck at 1.
3. Do exercise 5.13 through 5.15 on pages 406-407. You needn't be concerned about the difference between addiu and addi. For figures 5.35 and 5.43, use the versions in the errata, not the ones on the pages referred to in the exercises.

Instructor: Max Hailperin