Syllabus and general information for MCS-284: Computer Organization (Fall 2002)
MCS-284 will cover the architecture and organization of computer
hardware. We will look at the MIPS architecture as a representative
modern RISC architecture, and do some assembly language programming
for that architecture. We'll see how numbers are represented within a
computer and how the circuits that perform arithmetic operations on
those numerals are organized. With a high-level overview of digital
logic design to support us, we'll look at how the datapaths and
control circuits of processors are designed, and in particular we'll
look in some depth at pipelined processor design, which is the key
organizational principle at work in most present-day processors.
We'll examine the use of memory hierarchy (cache memory and virtual
memory) to provide the illusion of a large fast memory from the
reality of limited fast memory plus a larger but slower memory. We'll
look at input/output devices and buses, networking, and parallel computers.
Throughout the course there will be an emphasis on the quantitative
performance characteristics of computer systems; we'll look at the
influence of architecture and organization on performance, and take an
introductory look at the empirical and analytical tools appropriate to
the study of performance. Performance measurement will be one of the
main themes reinforced through the lab assignments; the other will be
assembly language programming.
I will be available in my office (OHS 303) from 11:30-12:20 on
Mondays, Wednesdays, and Fridays; from 1:30-2:20 on Tuesdays and
Thursdays; and by appointment. Or try your luck: just stop by and see
whether my door is open. You may send me electronic mail at firstname.lastname@example.org or call me at
extension 7466. I'll try to put any updates to my office hours on my
web page, so check there if in doubt.
World Wide Web
All course materials will be available through my World Wide Web page.
The URL for this course is http://www.gustavus.edu/~max/courses/F2002/MCS-284/.
After this syllabus I will give hardcopy handouts only to those
students who want them.
Our text will be the second edition of
Computer Organization and Design: The Hardware/Software
Interface by David A. Patterson and John L. Hennessy, published
by Morgan Kaufmann.
Normally labs will be held on Wednesdays and classes on the other four
days, but there are some exceptions; these are marked in the
syllabus. Labs will be held in the OHS 326 lab. Lab 0 will actually
be a special one-day demonstration experience not requiring a lab
report; only labs 1 through 4 will be ``real labs'' with reports.
Attendance is expected for all lab days. (If you turn in a lab
report early, you are excused from the remaining days devoted to that
lab.) I will excuse up to two absences per student, for any reason.
Use yours wisely. If you exceed this allowance, I may reduce your
course grade by one letter grade.
Homework assignment policy
I will assign a collection of homework problems for each chapter.
You may turn in any individual homework problem whenever you think you have it
solved. I will return it to you as quickly as I can, but normally
with only an indication of whether it is acceptable or needs more
work. (Sometimes I may give a brief indication of what area it needs
more work in.) If a problem needs more work, and you aren't sure what
sort of work it still needs, you should treat that as an invitation to
come talk with me about it. Once you've done the additional work, you
may turn the problem in again, attached to (or clearly marked on) the original. In fact, you may turn each problem
in as many times as you like, until it is marked as acceptable. Your
grade for the homework portion of the course will be based on the
fraction of homework problems that you eventually did acceptably.
Normally homework problems may be turned in at any time up until 8am
on October 8th for chapters 1-4 and appendices A and B, 8am on
November 11th for chapters 5 and 6, and 8am on December 13th for
chapters 7-9. However, if we would benefit from discussing a homework
problem in class, I may issue a "last call" for solutions to that
problem, at least a week in advance.
Unless I indicate that a particular problem must be done individually,
you may work on any problem in a group of two or three students.
One copy of the solution produced by the team should
be turned in, with all team members names on it. Write "we all
contributed fairly to this solution" and have all team members sign
under that statement.
There will be two intra-term tests and a final exam, as shown on the
In response to suggestions from previous years' students, I have moved
to evening exams in order to provide a less time-pressured test
format. The two intra-term exams will be conducted during the evening
from 7:00-8:30pm on October 10 and November 12, in Olin 317. Please let me
know as soon as possible if you won't be able to take the tests at
those times. In that case, I will be happy to set up another
hour and a half time block that works for you.
Students are encouraged to discuss the course, including issues raised
by the assignments. However, the solutions to assignments
should be individual original work unless otherwise specified. If an
assignment makes you realize you don't understand the material, ask a
fellow student a question designed to improve your understanding,
not one designed to get the assignment done. To do otherwise is to
cheat yourself out of understanding, as well as to be intolerably
Any substantive contribution to your solution by another person or
taken from a publication should be properly acknowledged in writing.
Failure to do so is plagiarism and will necessitate disciplinary
The same standards regarding plagiarism apply to team projects as to
the work of individuals, except that the author is now the entire team
rather than an individual. Anything taken from a source outside the
team should be be properly cited.
One additional issue that arises from the team authorship of
project reports is that all team members must stand behind all reports
bearing their names. All team members have quality assurance
responsibility for the entire project. If there is irreconcilable
disagreement within the team it is necessary to indicate as much in
the reports; this can be in the form of a ``minority opinion'' or
``dissenting opinion'' section where appropriate.
Late lab assignments
All lab assignments are due at the beginning of class on
the day indicated. Late assignments will be penalized by one ``grade
notch'' (such as A to A- or A- to B+) for each weekday late or fraction
thereof. However, no late assignments will be accepted after graded
assignments are handed back.
If you are too sick to complete an assignment on time, you
will not be penalized. Simply write ``late due to illness'' at the
top of the assignment, sign your name and hand it in. Other circumstances
will be evaluated on a case-by-case basis.
Please point out any arithmetic or clerical error I make in grading,
and I will gladly fix it. You may also request reconsideration if I
have been especially unjust.
The course components will contribute to your grade in the following
However, I reserve the right to
subjectively adjust your final grade. Please see me if you have any
question how you stand. Class participation is not graded; however,
it allows you to find and repair the gaps in your understanding before
doing the assignments, and thus can dramatically improve your grade.
You are responsible for all course material, whether or not you are
present when it was covered or distributed.
- Test 1: 15%
- Test 2: 15%
- Final exam: 20%
- Homework: 26% (based on fraction done: see above)
- Labs: 24% (4 @ 6% each)
All assignments should be readily readable, and should
not presuppose that I already know what you are trying to say. Use
full English sentences where appropriate (namely almost everywhere)
and clear diagrams, programs, etc. Remember that your goal is to
communicate clearly, and that the appearance of these technical items
plays a role in this communication process. Be sure your assignments
are always stapled together and that your name is always on them.
Please contact me immediately if you have a learning or physical
disability requiring accommodation.
A single number in the reading column means to read that entire
chapter. When a reading is indicated as going to a particular page
number, it means up to the first heading on that page. The same
section number on the next class day then indicates to finish the
This is my best guess as to the rate at which we will cover material.
However, don't be shocked if I have to pass out one or more revised
|9/4||Introduction (class instead of lab)||
|9/5||1||Computer abstractions and technology||
|9/9||article||More on performance||
|9/11||Lab 0: Under the hood||
|9/12||3.6-3.7||Procedures and strings in assembly||
|9/13||3.8-3.9||More on assembly programming||
|9/16||A.1-A.6,A.9||Assembly programming tools||
|9/17||3.10-3.11||Assembly programming examples||
|9/18||Lab 1: Elementary assembly programming||
|9/19||3.12-3.15||Yet more on assembly language||
|9/20||4.1-4.4||Two's complement, addition, and subtraction||
|9/23||More on arithmetic||
|9/24||4.5-p. 241||Arithmetic Logic Unit||
|9/25||Lab 1 (continued)||
|9/30||Lab 1 (concludes) (a Monday lab)||
|10/3||More on arithmetic||Lab 1
|10/8||Review; catch-up||HW chaps. 1-4,A,B
|10/9||Lab 2: More advanced assembly programming||
|10/10||Intra-term test 1, 7:00-8:30pm, OHS 317||
|10/11||5.1-5.2||A simple datapath||
|10/14||5.3-p. 371||A single-cycle processor||
|10/15||5.3||More on the single-cycle processor||
|10/16||Lab 2 (continued)||
|10/17||5.4||A multiple-cycle processor||
|10/22||More on the multiple-cycle processor||
|10/23||Lab 2 (continued)||
|10/28||6.2||A pipelined datapath||
|10/30||Lab 2 (concludes)||
|11/5||6.6||Branches and lab 3 preview||
|11/6||Lab 3: Measuring processor architectures' performance||
|11/7||6.8-6.9||Superscalar and advanced pipelining||
|11/8||6.10-6.12||More on pipelining||
|11/11||Review; catch-up||HW chaps. 5-6
|11/12||Intra-term test 2, 7:00-8:30pm, OHS 317||
|11/13||Lab 3 (continued)||
|11/15||Lab 3 (concludes) (a Friday lab)||
|11/18||7.3||Cache performance||Lab 3
|11/20||Lab 4: Cache simulation||
|11/22||7.6-7.9||Example memory hierarchies||
|11/25||Lab 4 (continued) (a Monday lab)||
|11/26||Lab 4 (continued) (a Tuesday lab)||
|11/27||8.1-8.3||Input/output devices (a Wednesday class)||
|12/4||Lab 4 (concludes)||
|12/5||More on networking||
|12/10||9.1-9.3||Bus-based MIMD architectures||Lab 4
|12/11||9.4-9.6||Network-based MIMD architectures (class instead of lab)||
|12/12||9.7-9.10||More on multiprocessors||
|12/13||Review; catch-up; evaluation||HW chaps. 7-9
Course web site: http://www.gustavus.edu/~max/courses/F2002/MCS-284/
Instructor: Max Hailperin <email@example.com>