MCS-284 Homework 6 (Fall 1999)
Due: November 9, 1999
Do exercise 6.9 on pages 530-531.
Suppose the MIPS instruction set architecture were changed to require
that the 16-bit displacement in load and store instructions always be
zero. (Any program that used non-zero displacements would have to be
How could the pipeline structure (as shown for example in figure 6.12,
page 452) be reconfigured to take advantage of this restriction?
(Don't feel limited to minor change; a major overhaul may be possible.)
What impact would your change have on the situation where a load is
followed by a use of the loaded value, as in figure 6.9, page 447?
If programs were rewritten to always have displacements of 0 and your
modified pipeline were used, which two of the three factors that
combine to determine performance (cycle time, CPI, and number of
instructions) would be most likely to change? Briefly explain the
cause for each of the two changes and indicate the direction in which
each of the two would change.
Instructor: Max Hailperin