MC48 Homework 8 (Fall 1996)
Due: December 13, 1996
Do exercise 8.5 on pages 655-6. The ``three cycle latency'' means a
three cyle period where the bus/memory system has to be left alone.
Even if there is no additional communication needed on the bus for
this memory access, the next memory access can't be started until
after the three idle cycles are over.
Do exercise 8.6 on page 656.
Do exercise 8.10 on page 656.
(This is exercise 8.n3.) What size messages would result in ATM
outperforming Ethernet by a factor of two, assuming latencies and
bandwidths were equivalent to those reported in the example on page
Instructor: Max Hailperin